• Room A415 - monday - 16:00 – 18:00
• xmatej@fi.muni.cz

• Úvod do VHDL
• Altera DE-2 - Cyclone II - EP2C35F672 - old Quartus II 13.0sp1
• Altera DE-1 - Cyclone V - SoC - Altera Quartus II 16.0

• Programmable structures fundamentals
• Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
• Designing in Verilog – combinational primitives, sequential circuits, state machine design
• FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice
• Prefabricated components – IP cores, Megafunctions
• Interfaces & Peripherals – RS232, LCD, keyboard
• Introduction to VHDL
• Sofcore computing – introduction to NIOS2 processor system

• Introducton PV200
• FPGA

• Altera Quartus + schematic
• Simulation tool - University program
• Full 1-bit adder - 2 half-adder → 2×2-bit adder
• quartus_ii_introduction1.pdf

• Verilog intro
• Example project DE-1 SoC Cyclone V
• DE-1 SoC Cyclon V - Quartus settings

• LAB 1 - Execrcise 1
• LAB 1 - Project example

• blocking / nonblocking - http://www.asic-world.com/tidbits/blocking.html
• reset - SYNCH/ASYNCH
• LAB 2 - Exercise 2
• LAB 1 - Solution
• LAB 2 - Solution
• Ex. 1 - Divider 50:50
• Ex. 2 - PWM generator - all LEDs
• Ex. 3 - change PWM duty cycle via BTN1 and BTN2 - 0 to 100 %
• Ex. 4 - Knight rider (3 LEDS - 100%; 50%; 20%) - MANDATORY homework
• ++ HEX counter nios_DE2_demo |

/**
 *  nios_DE2_demo -- demo design for Altera DE2 kit
 *    * Key0 act as reset
 *    * Key1 bliks red LED's
 *
 */
 
module nios_DE2_demo (
		CLK,
		KEY,
		SW,
		LEDG,
		LEDR,
		HEX0,
		HEX1
		);
 
	input CLK;
	input	[3:0]	KEY;
	input	[17:0]	SW;
	output [8:0]	LEDG;					
   output [17:0]	LEDR;
   output [6:0] HEX0;
	output [6:0] HEX1;
 
   wire div0, div1, div2;
   wire rst;
	reg [17:0] LEDS;
	reg [6:0] HEX;
	reg [8:0] LEDG;
 
	wire [3:0] number0w;
	reg [3:0] number0, number1;
 
	assign LEDR = LEDS;
	assign rst = KEY[0];
 
	clk_div divider0
(
	.CLK(CLK) ,	// input  CLK_sig
	.RST(rst) ,	// input  RST_sig
	.CLK_DIV(div0) 	// output  CLK_DIV_sig
);
 
	hex_7seg dsp0(number0, HEX0);
	hex_7seg dsp1(number1, HEX1);
 
   defparam divider0.divider = 50_000_000;
 
	always @ (div0) begin
		LEDG[1] <= div0;
	end
 
 
 
	always@(posedge CLK)
	if (!rst) begin
		number0 <= 0;
		number1 <= 0;
		LEDG[0] <= 0;
	end
	else if (div0) begin
		LEDG[0] <= !LEDG[0];
		if (number0 < 9) begin
			number0 <= number0 + 1;
		end
		else begin
			number1 <= number1 + 1;
			number0 <= 0;
		end
	end
 
 
endmodule

++

• ++ HEX counter hex_7seg |

module hex_7seg(hex_digit,seg);
 
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
 
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
 
always @ (hex_digit)
	case (hex_digit)
		4'h0: seg = 7'b1000000;
		4'h1: seg = 7'b1111001; 	// ---a----
		4'h2: seg = 7'b0100100; 	// |	  |
		4'h3: seg = 7'b0110000; 	// f	  b
		4'h4: seg = 7'b0011001; 	// |	  |
		4'h5: seg = 7'b0010010; 	// ---g----
		4'h6: seg = 7'b0000010; 	// |	  |
		4'h7: seg = 7'b1111000; 	// e	  c
		4'h8: seg = 7'b0000000; 	// |	  |
		4'h9: seg = 7'b0011000; 	// ---d----
		4'ha: seg = 7'b0001000;
		4'hb: seg = 7'b0000011;
		4'hc: seg = 7'b1000110;
		4'hd: seg = 7'b0100001;
		4'he: seg = 7'b0000110;
		4'hf: seg = 7'b0001110;
	endcase
endmodule

++

• FSM (Finite State Machine)
  • Verilog FSM
  • ++ Mealy |

    /* 4-State Mealy state machine
     
       A Mealy machine has outputs that depend on both the state and 
       the inputs.  When the inputs change, the outputs are updated
       immediately, without waiting for a clock edge.  The outputs
       can be written more than once per state or per clock cycle. */
     
    module mealy_mac
    (
    	input	clk, data_in, reset,
    	output reg [1:0] data_out
    );
     
    	// Declare state register
    	reg		[1:0]state;
     
    	// Declare states
    	parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
     
    	// Determine the next state synchronously, based on the
    	// current state and the input
    	always @ (posedge clk or posedge reset) begin
    		if (reset)
    			state <= S0;
    		else
    			case (state)
    				S0:
    					if (data_in)
    					begin
    						state <= S1;
    					end
    					else
    					begin
    						state <= S1;
    					end
    				S1:
    					if (data_in)
    					begin
    						state <= S2;
    					end
    					else
    					begin
    						state <= S1;
    					end
    				S2:
    					if (data_in)
    					begin
    						state <= S3;
    					end
    					else
    					begin
    						state <= S1;
    					end
    				S3:
    					if (data_in)
    					begin
    						state <= S2;
    					end
    					else
    					begin
    						state <= S3;
    					end
    			endcase
    	end
     
    	// Determine the output based only on the current state
    	// and the input (do not wait for a clock edge).
    	always @ (state or data_in)
    	begin
    		case (state)
    			S0:
    				if (data_in)
    				begin
    					data_out = 2'b00;
    				end
    				else
    				begin
    					data_out = 2'b10;
    				end
    			S1:
    				if (data_in)
    				begin
    					data_out = 2'b01;
    				end
    				else
    				begin
    					data_out = 2'b00;
    				end
    			S2:
    				if (data_in)
    				begin
    					data_out = 2'b10;
    				end
    				else
    				begin
    					data_out = 2'b01;
    				end
    			S3:
    				if (data_in)
    				begin
    					data_out = 2'b11;
    				end
    				else
    				begin
    					data_out = 2'b00;
    				end
    		endcase
    	end
     
    endmodule

++

• ++ Moore |

// 4-State Moore state machine
 
// A Moore machine's outputs are dependent only on the current state.
// The output is written only when the state changes.  (State
// transitions are synchronous.)
 
module moore_mac
(
	input	clk, data_in, reset,
	output reg [1:0] data_out
);
 
	// Declare state register
	reg		[1:0]state;
 
	// Declare states
	parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
 
	// Output depends only on the state
	always @ (state) begin
		case (state)
			S0:
				data_out = 2'b01;
			S1:
				data_out = 2'b10;
			S2:
				data_out = 2'b11;
			S3:
				data_out = 2'b00;
			default:
				data_out = 2'b00;
		endcase
	end
 
	// Determine the next state
	always @ (posedge clk or posedge reset) begin
		if (reset)
			state <= S0;
		else
			case (state)
				S0:
					state <= S1;
				S1:
					if (data_in)
						state <= S2;
					else
						state <= S1;
				S2:
					if (data_in)
						state <= S3;
					else
						state <= S1;
				S3:
					if (data_in)
						state <= S2;
					else
						state <= S3;
			endcase
	end
 
endmodule

++

• ++ Save FSM |

// Safe state machine
 
module safe_state_machine
(
	input	clk, data_in, reset,
	output reg [1:0] data_out
);
 
	// Declare the state register to be "safe" to implement
	// a safe state machine that can recover gracefully from
	// an illegal state (by returning to the reset state).
	(* syn_encoding = "safe" *) reg [1:0] state;
 
	// Declare states
	parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
 
	// Output depends only on the state
	always @ (state) begin
		case (state)
			S0:
				data_out = 2'b01;
			S1:
				data_out = 2'b10;
			S2:
				data_out = 2'b11;
			S3:
				data_out = 2'b00;
			default:
				data_out = 2'b00;
		endcase
	end
 
	// Determine the next state
	always @ (posedge clk or posedge reset) begin
		if (reset)
			state <= S0;
		else
			case (state)
				S0:
					state <= S1;
				S1:
					if (data_in)
						state <= S2;
					else
						state <= S1;
				S2:
					if (data_in)
						state <= S3;
					else
						state <= S1;
				S3:
					if (data_in)
						state <= S2;
					else
						state <= S3;
			endcase
	end
 
endmodule

++

• Exercise:
  • 10 s coutdown with 7-segment (down counter → 7-segment decoder)
  • on the end - blinking RED LEDs
  • reset - BTN1
  • ADD: set initial value using hold the first button, then start pressing the second button

• vhdl_en.pdf
  • solution
• vhdl_cz.pdf
• vhdl_de2_init.zip
• vhdl_ref_manual.pdf

Nios II/f

• The Nios II/f core is designed for maximum performance at the expense of core size. Features of Nios II/f include:
  • Separate instruction and data caches (512 B to 64 kB)
  • Optional MMU or MPU
  • Access to up to 2 GB of external address space
  • Optional tightly coupled memory for instructions and data
  • Six-stage pipeline to achieve maximum DMIPS/MHz
  • Single-cycle hardware multiply and barrel shifter
  • Optional hardware divide option
  • Dynamic branch prediction
  • Up to 256 custom instructions and unlimited hardware accelerators
  • JTAG debug module
  • Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

• de1-soc_computer_niosii.pdf
• de1-soc_computer_arm.pdf
• niosii_hw_dev_tutorial.zip
• NIOS II example
• Altera DE2 exmples - system 1.6

• Dlhopolcek - Audio efekty + NIOS II
• Novacik - Snake (+ NIOS II)
• Paral - Snake + PS2 keyboard + NIOS II
• Barna - MD5
• Obetko - IRDA - copy of remotre control
• van Hoef - ethernet remote control

• LAB 7 - FSM
• LAB 8 - Memmory

• vhdl_introduction_to_ver12_v5_0.ppt
• vhdl_ii_cz.pdf

• nios2_hardware_tutorial.pdf
• niosii_hw_dev_tutorial.zip
• NIOS II example
• {{:pv200:de2_system_v1.6.zip|Altera DE2 exmples - system 1.6}

• simulation tools (Modelsim)
• logic analyser

• 16-bit softcore CPU - Salvet
• Delta-deciballity solder - Pastva
• Serial communication + LCD - Deniz
• LCD screen + serial communication as graphical terminal - Sedat
• audio filter - Stanka

• MD5 cracker
• video filters
• audio filters
• ethernet analyzer
• graphical efects on LCD screen (fractal…)
• PS2 + LCD
• logic analyser
• snake, pacman…
• GPS receiver
• IRDA communication
• …